1. Field of the Invention
This invention relates to semiconductor devices and more particularly to flash memory cells.
2. Description of Related Art
U.S. Pat. No. 4,780,424 of Holler et al "Process for Fabricating Electrically Alterable Floating Gate Memory Devices" shows a tunnel oxide in an EPROM cell.
The limitations of conventional flash memory cells is that the size of a Mask ROM cannot be shrunk. Secondly, there is a problem of over erasure, i.e. sometimes the erase action in one cell affects a neighboring (adjacent) cell. Thirdly, a relatively high voltage multiple voltage level power supply which requires relatively high power levels with a voltage of greater than 7 Volts.
In the past hot electrons have been a problem. In Uyemura "Circuit Design for CMOS VLSI," pp. 66-69 it is stated that "Hot electron effects have been observed in MOSFET's, particularly in devices with channel lengths smaller than 1 micron. Standard transistors can be degraded by tunnelling effects . . . . Highly energetic particles can leave the silicon and enter the gate oxide. Trapped electrons increase the oxide charge Q.sub.ox, leading to instability of the threshold voltage. Long-term reliability problems may result from this mechanism. In addition, hot electrons may induce leakage gate current I.sub.g and excessive substrate current I.sub.s." The use of LDD (Lightly Doped Drain) structures have been used to overcome the problem of hot electrons.